Universal Makefile

This is just a basic starting point for compiling a C project.

TARGET = theapp
SOURCES = $(wildcard *.c)
OBJECTS = $(subst .c$,.o,$(SOURCES))
HEADERS = $(wildcard *.h)
CC = gcc
LINK = gcc
STRIP = strip

$(TARGET): .depend $(OBJECTS)
        echo "#define BUILD_HOST \"`hostname -f`\"" > build_host.h
        $(LINK) $(LFLAGS) -o $(TARGET) $(OBJECTS) $(LIBPATH) $(LIBS)
        $(STRIP) $(TARGET)

.c.o: $*.h common.h
        $(CC) -c $(CFLAGS) $(DEBUGFLAGS) $(INCPATH) -o $@ $<

-include .depend

build_host.h:
        echo "#define BUILD_HOST \"`hostname -f`\"" > build_host.h

clean:
        -rm -f .depend
        -rm -f $(OBJECTS)
        -rm -f *~ core *.core
        -rm -f version.h
        -rm -f $(TARGET)

depend:
.depend: Makefile $(SOURCES) $(HEADERS)
        @if [ ! -f .depend ]; then touch .depend; fi
        @makedepend -Y -f .depend  $(SOURCES) 2>/dev/null

test:
        echo $(OBJECTS)